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TB6613FTG 2012-01-30 1 toshiba bicd integrated circuit silicon monolithic TB6613FTG dc and stepping motor driver the TB6613FTG is a dc motor driver ic using ldmos output transistors with low on-resistance. the TB6613FTG incorporates five pwm constant-current h-bridge drivers, of which four drivers can be used for micro stepping motor drives of up to two stepping motors. the TB6613FTG is best suited to control various lens actuators in digital still cameras. the three-wire serial interface pr ovides control over the drivers, thus reducing the number of lines required for interfacing with the control ic. features ? motor power supply voltage: vm 6 v (max) ? control power supply voltage: v cc = 3 v to 5.5 v ? output current: i out 0.8 a (max) ? complementally p- and n-cha nnel ldmos output transistors ? output on-resistance: r on (upper and lower sum) = 1.5 ? (@vm = v cc = 5 v typ.) channels a, b, c and d ? four h-bridge drivers capable of pwm constant-current control supports up to two two-phase bipolar stepping motors (stms) or up to four actuators. ? each channel is individually configur able for either h-bridge mode or stm step mode via the serial interface. ? in stm step mode, the micro stepping resolution is selectabl e from 6 bits (256 steps per full cycle) or 1 bit (8 steps per full cycle). channel e ? one pwm constant-current driver ? the constant-current reference voltage (vref) is programmable via the internal 6-bit dac. other features ? each channel has a dac for setting constant-current va lues (channels a to d = 2 bits in h-bridge mode and 2 bits 6 bits in step mode; channel e = 6 bits) ? dedicated standby (power-save) pin ? thermal shutdown (tsd) ? undervoltage lockout (uvlo): resets and disables the internal circuitry when v cc falls below 2.2 v (typ.). ? small vqon44 package (0.4-mm lead pitch) note: this product has a mos structure and is sensitive to electrostatic discharge. when handling this product, ensure that the environment is pr otected against electrostatic disc harge by using an earth strap, a conductive mat and an ionizer. ensure also that the ambient temperature and relative humidity are maintained at reasonable levels. weight: 0.05 g (typ.)
TB6613FTG 2012-01-30 2 block diagram standby mck 33 pwma /ck1 uvlo (2.2 v) 2-bit dac1 v ref (0.3 v) 1/n 5 v cc a o1 a o2 vm1 rfa pwm timer pre- driver 31 36 34 h-bridge a h-bridge control 35 bo2 rfb pwm timer pre- driver 39 37 h-bridge control 38 bo1 co1 co2 vm2 rfc pwm timer pre- driver 25 20 22 h-bridge control 21 do2 rfd pwm timer pre- driver 17 19 h-bridge d h-bridge control 18 do1 eo1 eo2 vm3 rfe pwm timer pre- driver 3 42 40 h-bridge e h-bridge control 41 tsd fo2 pgnd1 pre- driver 1 43 h-bridge f h-bridge control fo1 44 h-bridge b h-bridge c go2 pgnd2 pre- driver 15 16 h-bridge g h-bridge control go1 14 9 ho2 pre- driver 12 13 h-bridge h h-bridge control ho1 vm4 step decoder 1 6-bit dac step decoder 2 6-bit dac 8 stby 12-bit serial decoder 7 gnd 29 ld 27 data 28 ck 2-bit dac2 6-bit dac 1/n 1/n 6 mo1 30 32 pwmb /en1 23 pwmc /ck2 mo2 26 24 pwmd /en2 pwme 4 pwmf 2 pwmg 10 pwmh 11
TB6613FTG 2012-01-30 3 pin function no. pin name i/o function 1 fo1 o channel-f output 1 2 pwmf i pwm signal input (channel f) 3 vm3 D motor power supply 3 (channels e and f) 4 pwme i pwm signal input (channel e) 5 v cc D power supply 6 mck i clock input for constant-current control 7 gnd D ground 8 stby i standby (power-save) control 9 vm4 D motor power supply 4 (channels g and h) 10 pwmg i pwm signal input (channel g) 11 pwmh i pwm signal input (channel h) 12 ho1 o channel-h output 1 13 ho2 o channel-h output 2 14 pgnd2 D motor ground 2 (channels g and h) 15 go1 o channel-g output 1 16 go2 o channel-g output 2 17 do1 o channel-d output 1 18 rfd D connection pin for a current-s ensing resistor (channel d) 19 do2 o channel-d output 2 20 co1 o channel-c output 1 21 rfc D connection pin for a current-s ensing resistor (channel c) 22 co2 o channel-c output 2 23 pwmc/ck2 i pwm signal input (channel c)/ step clock input 2 24 pwmd/en2 i pwm signal input (channel d)/stm enable input 2 25 vm2 D motor power supply 2 (channels c and d) 26 mo2 o stm electrical degree monitor output 2, open-drain output, need ext. pull-up resistor 27 data i serial data input 28 ck i serial clock input 29 ld i serial load enable 30 mo1 o stm electrical degree monitor output 1, open-drain output, need ext. pull-up resistor 31 vm1 D motor power supply 1 (channels a and b) 32 pwmb/en1 i pwm signal input (channel b)/stm enable input 1 33 pwma/ck1 i pwm signal input (channel a)/ step clock input 1 34 ao2 o channel-a output 2 35 rfa D connection pin for a current-s ensing resistor (channel a) 36 ao1 o channel-a output 1 37 bo2 o channel-b output 2 38 rfb D connection pin for a current-s ensing resistor (channel b) 39 bo1 o channel-b output 1 40 eo2 o channel-e output 2 41 rfe D connection pin for a current-s ensing resistor (channel e) 42 eo1 o channel-e output 1 43 fo2 o channel-f output 2 44 pgnd1 D motor ground 1 (channel f)
TB6613FTG 2012-01-30 4 absolute maximum ratings (ta = 25c) characteristics symbol rating unit remarks supply voltage v cc 6 v v cc motor supply voltage vm 6 v vm v out ? 0.2 to 6 v channels a to h output voltage v mo v cc v mo1, mo2 (open-drain) i out 0.8 a channels a to h output current i mo 1 ma mo1, mo2 (open-drain) input voltage v in ? 0.2 to 6 v control input pins power dissipation p d 4.17 w note operating temperature t opr ? 20 to 85 c storage temperature t stg ? 55 to 150 c note: when mounted on a single-side glass epoxy pcb (size: 76.4 mm 114.3 mm 1.6 mm) with a 40% dissipating copper surface. operating conditions 1 (ta = ? 20 to 85c) rating characteristics symbol min typ. max unit remarks supply voltage for small-signal circuitry v cc 3 3.3 5.5 v motor supply voltage vm 2.5 D 5.5 v D D 600 vm = 3 to 5.5 v output current i out D D 250 ma 2.2 v vm 3 v pwm frequency f pwm D D 100 khz master clock frequency f mck D 1 5 mhz
TB6613FTG 2012-01-30 5 operating conditions 2: serial data controller (ta = ? 20c to 85c) rating characteristics symbol min max unit clock pulse width low t ckl 200 D ns clock pulse width high t ckh 200 D ns clock rise time t cr D 50 ns clock fall time t cf D 50 ns data setup time t dch 30 D ns data hold time t chd 60 D ns ck to ld rising edge t chl 200 D ns ld to pwm delay t ldc2 100 D ns load pulse width high t ldh 2 D s ck frequency f clk D 2.5 mhz t ldh t chl t dch ld latch t ldc2 pwm ck t c r t ckl data t chd t ckh t cf
TB6613FTG 2012-01-30 6 principle of operation bridge outputs: channels a through h pwm control in pwm constant-current mode, the pwm chopper circuit alternates between on (t1, t5) and short brake (t3). (to eliminate shoot-through current, a dead time (t2, t4 ) of 50 ns (design target only) is inserted when the pwm is turned on and off.) m vm out2 out1 t4 gnd m vm out2 out1 t5 gnd m gnd out2 out1 t3 m gnd out2 out1 t2 m gnd out2 out1 t1 vm gnd output voltage waveform (out1) t1 t5 t3 t2 t4 vm vm vm
TB6613FTG 2012-01-30 7 constant current control on h-bridge dri ver; off-time fixed pwm constant current chopping operation TB6613FTG operates constant current cont rol with off-time-fixed pwm operation. the chop-off time is fixed by counting internally the external input driving clock, so the chop-off time could be adjusted by changing the frequency of driving clock or the number of internal counting (2, 4, 6, 8 counts(4steps) are selectable). first, motor coil current is generated on chop -on starting, and when the voltage (vrf) on external current-sensing resistor rise and reach the reference voltage vlimit (means current limit le vel) the current is to off on comparator operation. the chop-off time is fixed with 4bits of internal clock co unting from the first rising edge of internal clock just after the output high-side tran sistor is turned off. (the counter is reset on the fifth ri sing edge of the internal clock) this chop-off time control generates the pwm si gnal to drive on/off th e output transistors. timing diagram of the pwm constant-current chopper circuit with a turn-off period of four clock cycles 1 2 3 decay on on power on power of f internal clock off time r (counter) generated pwm signal vlimit coil current counts 4 rising edges of internal clock. (the upper limit of the coil current (io peak ) can be calculated as: io = vlimit/rnf.) 4 5 6 decay on decay on vrf
TB6613FTG 2012-01-30 8 micro step control: ch annels a, b, c and d in pwm constant-current mode, when the TB6613FTG gene rates a pwm signal, it measures a constant turn-off period by counting the number of rising edges of the internal clock signal (divided clock of mck). ? pulse clock control: the TB6613FTG steps up the current at each rising edge of the clock input to the pwma/ck1 (for channels a and b) or pwmc/ck2 (for channels c and d) pin. (current step-ups actually occur synchronous to the internal clock signal derived from mck.) ? step modes: selectable from the following two modes: 1-bit mode: 8 steps per full cycle 6-bit mode: resolution = 256 steps per full cycle ? enable control: setting pwmb/en1 (for channels a and b) or pwmd/en2 (for channels c and d) high and low enables and disables motor excitation. enn = 1: excitation enabled; enn = 0: excitation disabled ? current decay modes: in stm step mode, the motor current recircu lates back to the power supply in fast-decay mode when the vref level chan ges during current step-down. the current decay rate is selectable from four modes. ? electrical degree monitor: as the outp ut current increases or decreases in steps with the ck input, a negative pulse is generated from the mo1 (or mo2) pin at every 90 or 360 electrical degrees. ? pwm chopping frequency: the pwm signal is generated by dividing the external mck signal by up to 31, as programmed in a 5-bit register. ? turn-off period: the turn-off period is selectable from 2, 4, 6 and 8 cycles of the internal clock signal, which is generated by dividing mck internally. cw/ccw, excitation enable, pwm ck m 64 64 step decoder 6-bit dac ph. b ph. a 63 63 62 62 2 2 1 1 pwm time r pre- driver h-bridge a phase a m pwm time r pre- driver h-bridge b phase b 2-bit dac vref (0.3 v) serial decoder 5-bit divider 1/1 to 1/31 data ld mck (1 mhz) mo1 pwmb /en1 pwma /ck1 vm pgnd
TB6613FTG 2012-01-30 9 ? constant-current setting: the maximum vref voltage can be selected from 0.3 v, 0.225 v, 0.15 v and 0.075 v with a 2-bit dac based on the 0.3-v on-chip reference voltage. this dac output is divided by the 6-bi t dac under control of the micro step decoder to establish vref fo r constant-current control. current decay mode: only applicable for step-down control in stm step mode in stm step mode, the output current step-down slope may not match the changes of the target current level specified by vref depending on the time constant of a moto r coil, thus leading to a big distortion from the desired output current waveform. to improve the matching between th e output current and the target cu rrent level, the TB6613FTG enters fast-decay mode very briefly immediately after each vref step-down. in this mode, the output current recirculates back to the power supply. the fast-decay time is generated by counting the intern al clock signal and selectable from the four modes listed below: fast-decay mode number of internal clock cycle decay rate fast0 0 no fast1 1 small fast2 2 medium fast3 3 large
TB6613FTG 2012-01-30 10 current step-up slope current step-down slope (when in fast1 mode) 1 2 3 4 5 1 2345 1234 5 1 2 3 4 internal clock vre f charge mode slow-decay mode enters charge mode at the vref step-up edge 1 2 3 4 5 1 2345 1 2 3 4 5 1 2 3 internal clock vre f charge mode slow-decay mode enters fast-decay mode at the vref step-down edge 12 fast-decay mode
TB6613FTG 2012-01-30 11 timing diagram of micro step operation with 1-bit resolution (8 steps per full cycle) output current vector ckn 100 71 0 ? 71 ? 100 i o (%) mon init mon quarte r a b 100 0 71 71 100 ib (%) ia (%) 1-2-phase excitation 0
TB6613FTG 2012-01-30 12 timing diagram of micro step operation with 6-bit resolution (256 steps per full cycle) 0 64 128 192 256 b a 0 64 128 192 ckn mon init mon quarte r 100 90 80 70 60 50 40 30 20 10 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 10 i o (%)
TB6613FTG 2012-01-30 13 relationship between the enable and reset inputs and output signals enable (enn pin) setting the enn signal low disables on ly the output block, and the internal circuitry continues to operate in accordance with the ckn input. therefore, when the enn signal is set high again, the output current restarts as if phases had pr oceeded with the ckn signal. when enn = low, the output signals are disabled regardless of the state of the reset signal. setting the reset signal low while enn = low resets the counter. reset (serial command) setting the reset signal high causes the outputs to be put in the initial state and the mon output to be driven low. when the reset signal goes is set low again, the output current genera tion restarts from the initial state at the next rising edge of ckn. ckn 0 71 100 (%) ? 71 ? 100 i a t 0 t 1 t 2 t 3 off t 7 t 8 t 9 t 10 t 11 t 12 enn reset mon reverse forward ckn 0 71 100 (%) ? 71 ? 100 i a t 0 t 1 t 2 t 3 t 3 t 4 t 5 t 6 t 7 t 8 enable reset t 2 reverse forward mon
TB6613FTG 2012-01-30 14 input pins all input pins (ck, data, ld, pwma/ck1, pwmb/en1, pwmc/ck2, pwmd/e n2, pwme, pwmf, pwmg, pwmh, stby, mck) have a pull-down resister of about 200 k ? . gnd 200 k ? input
TB6613FTG 2012-01-30 15 serial data format 12-bit serial data first last d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 selector (4 bits) data register organizations d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address 0 0 0 0 mod1 stm1 if1 ick1: 5 bits 0 0 0 0 1 2-bit dac1 mdr1 rst1 mo1 off1 D 1 0 0 1 0 p1a p1b sdfst1 scw1 D D D 2 0 0 1 1 mod2 p2a p2b if2 off2 D D 3 0 1 0 0 mod3 stm3 if3 ick3: 5 bits 4 0 1 0 1 2-bit dac2 mdr3 rst3 mo3 off3 D 5 0 1 1 0 p3a p3b sdfst3 scw3 D D D 6 0 1 1 1 mod4 p4a p4b if4 off4 D D 7 1 0 0 0 mod5 if5 6-bit dac 8 1 0 0 1 off5 D ick5: 5 bits 9 1 0 1 0 p5a p5b D D D D D D 10 1 0 1 1 mod6 p6a p6b D D D D D 11 1 1 0 0 mod7 p7a p7b D D D D D 12 1 1 0 1 mod8 p8a p8b D D D D D 13 1 1 1 0 14 1 1 1 1 don?t access 15 modx : h-bridge control 0 = direct pwm mode (table 1) 1 = control mode of table 2 (all channels) stmx : stm mode select 0 = h-bridge mode 1 = stm step mode (*) ifx : constant-current control 0 = constant-current control disabled 1 = constant-current control enabled (channels a, b, c, d and e) * valid only in h-bridge mode (stmx = 0). constant-current control is always enabled in stm step mode. 2-bit dacx : 2-bit dac setting 0 = 0.075 v; 1 = 0.15 v; 2 = 0.225 v; 3 = 0.3 v 4 levels in 0.075-v steps (*) ickx : divide ratio for internal clock* divide s the external mck by 1 to 31. (*, channel e) mdrx : stm excitation mode 0 = step mode with 6-bit resolution 1 = 1-2-phase excitation mode (*) ck data ld latch
TB6613FTG 2012-01-30 16 sdfstx : fast-decay mode specifies the fast -decay time in number of internal clock cycles: 0 = no fast-decay cycle; 1 = 1 cycle; 2 = 2 cycles; 3 = 3 cycles (*) scwx : stm rotation direction select 0 = forward; 1 = reverse (*) rstx : stm step counter reset 0 = count mode; 1 = reset (*) mox : monitor signal interval 0 = every 360 electrical degree 1 = every 90 electrical degree (*) offx : pwm turn-off period specifies the pwm turn-off period in number of internal clock cycles: 0 = 2 cycles; 1 = 4 cycles; 2 = 6 cycles; 3 = 8 cycles (*, channel e) pxa : h-bridge control input a see tables 1 and 2 on next page (all channels) pxb : h-bridge control input b see tables 1 and 2 on next page (all channels) 6-bit dac : channel-e 6-bit dac setting* msb = 0.3 v (6 bits) (channel e) note: two registers at addresses 3 and 7 are only valid in h-bridge mode (stmx = 0). *: detailed descriptions of register settings are provided in the tables on the following pages. **: do not access to address-14 or address-15 as these are for ic-testing in toshiba.
TB6613FTG 2012-01-30 17 supplemental register descriptions 1. each channel or micro step pair is separately addressed. address corresponding channels 0, 1, 2, 3 channels a and b (stm1 = 1: micro step pair 1 (a&b)) 4, 5, 6, 7 channels c and d (stm3 = 1: micro step pair 2 (c&d)) 8, 9, 10 channel e 11 channel f 12 channel g 13 channel h note: two registers at addresses 3 (channel-b setting) and 7 (channel-d setting) are only valid in h-bridge mode (stmx = 0). 2. the character x in register names represents a channel number. x corresponding channels x = 1 channel a (the settings of stmx, ickx, 2-bit dacx, md rx, rstx, mox, sdfstx and scwx are shared between channels a and b.) x = 2 channel b x = 3 channel c (the settings of stmx, ickx, 2-bit dacx, mdrx, rstx, mox, sdfstx and scwx are shared between channels c and d.) x = 4 channel d x = 5 channel e x = 6 channel f x = 7 channel g x = 8 channel h
TB6613FTG 2012-01-30 18 3. ickx: setting the divide ratio for the external mck used to generate the internal clock the external mck is divided to generate an internal clock, as specified for each channel (micro step pair) by d4, d3, d2, d1 and d0 at addresses 0 (for channels a and b), 4 (for channels c and d) and 8 (for channel e). address 0, 4 or 8 decimal binary d4 d3 d2 d1 d0 divide ratio for internal clock 1 00001 0 0 0 0 1 1/1 2 00010 0 0 0 1 0 1/2 3 00011 0 0 0 1 1 1/3 4 00100 0 0 1 0 0 1/4 5 00101 0 0 1 0 1 1/5 6 00110 0 0 1 1 0 1/6 7 00111 0 0 1 1 1 1/7 8 01000 0 1 0 0 0 1/8 9 01001 0 1 0 0 1 1/9 10 01010 0 1 0 1 0 1/10 11 01011 0 1 0 1 1 1/11 12 01100 0 1 1 0 0 1/12 13 01101 0 1 1 0 1 1/13 14 01110 0 1 1 1 0 1/14 15 01111 0 1 1 1 1 1/15 16 10000 1 0 0 0 0 1/16 17 10001 1 0 0 0 1 1/17 18 10010 1 0 0 1 0 1/18 19 10011 1 0 0 1 1 1/19 20 10100 1 0 1 0 0 1/20 21 10101 1 0 1 0 1 1/21 22 10110 1 0 1 1 0 1/22 23 10111 1 0 1 1 1 1/23 24 11000 1 1 0 0 0 1/24 25 11001 1 1 0 0 1 1/25 26 11010 1 1 0 1 0 1/26 27 11011 1 1 0 1 1 1/27 28 11100 1 1 1 0 0 1/28 29 11101 1 1 1 0 1 1/29 30 11110 1 1 1 1 0 1/30 31 11111 1 1 1 1 1 1/31
TB6613FTG 2012-01-30 19 4. 6-bit dac: setting the 6-bit dac for channel e the vref voltage that determines the target current level for constant-current control of channel e can be specified by d5, d4, d3, d2, d1 and d0 at address 8. the target current level is determin ed by this voltage level and the ex ternal current sensing resistor. address 8 decimal binary d5 d4 d3 d2 d1 d0 voltage (mv) 0 000000 0 0 0 0 0 0 0.0 1 000001 0 0 0 0 0 1 4.8 2 000010 0 0 0 0 1 0 9.5 3 000011 0 0 0 0 1 1 14.3 4 000100 0 0 0 1 0 0 19.0 5 000101 0 0 0 1 0 1 23.8 6 000110 0 0 0 1 1 0 28.6 7 000111 0 0 0 1 1 1 33.3 8 001000 0 0 1 0 0 0 38.1 9 001001 0 0 1 0 0 1 42.9 10 001010 0 0 1 0 1 0 47.6 11 001011 0 0 1 0 1 1 52.4 12 001100 0 0 1 1 0 0 57.1 13 001101 0 0 1 1 0 1 61.9 14 001110 0 0 1 1 1 0 66.7 15 001111 0 0 1 1 1 1 71.4 16 010000 0 1 0 0 0 0 76.2 17 010001 0 1 0 0 0 1 81.0 18 010010 0 1 0 0 1 0 85.7 19 010011 0 1 0 0 1 1 90.5 20 010100 0 1 0 1 0 0 95.2 21 010101 0 1 0 1 0 1 100.0 22 010110 0 1 0 1 1 0 104.8 23 010111 0 1 0 1 1 1 109.5 24 011000 0 1 1 0 0 0 114.3 25 011001 0 1 1 0 0 1 119.0 26 011010 0 1 1 0 1 0 123.8 27 011011 0 1 1 0 1 1 128.6 28 011100 0 1 1 1 0 0 133.3 29 011101 0 1 1 1 0 1 138.1 30 011110 0 1 1 1 1 0 142.9 31 011111 0 1 1 1 1 1 147.6 32 100000 1 0 0 0 0 0 152.4 33 100001 1 0 0 0 0 1 157.1 34 100010 1 0 0 0 1 0 161.9 35 100011 1 0 0 0 1 1 166.7 36 100100 1 0 0 1 0 0 171.4 37 100101 1 0 0 1 0 1 176.2 38 100110 1 0 0 1 1 0 181.0
TB6613FTG 2012-01-30 20 address 8 decimal binary d5 d4 d3 d2 d1 d0 voltage (mv) 39 100111 1 0 0 1 1 1 185.7 40 101000 1 0 1 0 0 0 190.5 41 101001 1 0 1 0 0 1 195.2 42 101010 1 0 1 0 1 0 200.0 43 101011 1 0 1 0 1 1 204.8 44 101100 1 0 1 1 0 0 209.5 45 101101 1 0 1 1 0 1 214.3 46 101110 1 0 1 1 1 0 219.0 47 101111 1 0 1 1 1 1 223.8 48 110000 1 1 0 0 0 0 228.6 49 110001 1 1 0 0 0 1 233.3 50 110010 1 1 0 0 1 0 238.1 51 110011 1 1 0 0 1 1 242.9 52 110100 1 1 0 1 0 0 247.6 53 110101 1 1 0 1 0 1 252.4 54 110110 1 1 0 1 1 0 257.1 55 110111 1 1 0 1 1 1 261.9 56 111000 1 1 1 0 0 0 266.7 57 111001 1 1 1 0 0 1 271.4 58 111010 1 1 1 0 1 0 276.2 59 111011 1 1 1 0 1 1 281.0 60 111100 1 1 1 1 0 0 285.7 61 111101 1 1 1 1 0 1 290.5 62 111110 1 1 1 1 1 0 295.2 63 111111 1 1 1 1 1 1 300.0 note: the voltage values are typical values.
TB6613FTG 2012-01-30 21 function tables the drive method in h-bridge mode (stmx = 0) can be selected from tables 1 and 2, via the modx bit. (channels e, f, g and h are always in h-bri dge mode regardless of the stmx setting.) table 1 modx = 0, stmx = 0 pxa pxb pwmx outxa outxb drive mode 0 0 x z z stop 0 1 l l l short brake 0 1 h l h reverse 1 0 l l l short brake 1 0 h h l forward 1 1 x l l short brake table 2 modx = 1, stmx = 0 pxa pxb pwmx outxa outxb drive mode 0 x x z z stop 1 0 l h l forward 1 0 h l h reverse 1 1 x l l short brake function table: stby pin, uvlo and tsd ci rcuitry, rstx bit (internal register) function stby (note 1) uvlo tsd rstx internal register cleared cleared not affected not affected driver turned off turned off turned off turned on (controlled by the enn pin) note 1: stby: l = standby (power-save) mode; h = normal operation mode note : all registers are cleared to zero.
TB6613FTG 2012-01-30 22 power supply sequence the power supply sequence for TB6613FTG is required for proper operation. the power up sequence between vcc and vmx(x=1,2,3,4) is shown below. vcc vmx on on over 100ns vmx(x=1,2,3,4) must be supplied after waiting over 100ns period from the vcc is supplied. if vmx are supplied without the waiting time or vcc supply, ic could not start the normal operation and go into some error mode in a case. data communication initialization sequence a proper initialization sequence is also needed for a host to communicate with TB6613FTG. the initialization sequence is shown below.
TB6613FTG 2012-01-30 23 electrical characteristics (v cc = 3.3 v, vm = 5 v, ta = 25c, unless otherwise specified.) characteristics symbol test condition min typ. max unit i cc all 8 channels in forward mode D 2 4 ma i cc (stb) D 0.1 10 supply current i m (stb) standby mode (stby = 0 v) D 0 1 a v inh v cc 0.7 D v cc + 0.2 input voltage v inl ? 0.2 D v cc 0.3 v i inh v ih = 3 v 5 15 25 serial, stby, pwm and clk inputs input current i inl v il = 0 v D D 1 a i o = 0.2 a, v cc = 5 v D 0.3 0.4 output saturation voltage (channels a to h) v sat (u + l) i o = 0.6 a, v cc = 5 v D 0.9 1.2 v i l (u) D D 1 output leakage current (channels a to h) i l (l) vm = 6 v D D 1 a v f (u) D 1 D output diode forward voltage v f (l) i f = 0.6 a (design target only) D 1 D v voltage comparator offset for constant-current control comp ofs rf = 0.5 ? , vref = 0.1 v (including dac) ? 10 D 10 mv nonlinearity lb ? 3 D 3 6-bit dac differential linearity error dlb channel e ? 2 D 2 lsb 6-bit mode see appendix on next page. D D D micro step reference level 1-bit mode half step (design target only) D 71 D % uvlo trip threshold uvld D 2.0 D v cc under voltage lockout (uvlo) uvlo recovery uvlc (design target value) D 2.2 D v thermal shutdown threshold tsd D 170 D thermal shutdown hysteresis tsd (design target only) D 20 D c delay between vcc to vmx td1 (design target only) vcc, vm1,2,3,4 D 100 D delay between stby=h to serial communication td2 (design target only) stby, ck, data, ld D 100 D ns
TB6613FTG 2012-01-30 24 appendix: micro step reference level wi th 6-bit resolution (design target only) min typ. max unit min typ. max unit 63 D 100 D 31 D 71 D 62 D 100 D 30 D 69 D 61 D 100 D 29 D 67 D 60 D 100 D 28 D 65 D 59 D 100 D 27 D 63 D 58 D 99.5 D 26 D 61.25 D 57 D 99 D 25 D 59.5 D 56 D 98.5 D 24 D 57.75 D 55 D 98 D 23 D 56 D 54 D 97.5 D 22 D 53.75 D 53 D 97 D 21 D 51.5 D 52 D 96.5 D 20 D 49.25 D 51 D 96 D 19 D 47 D 50 D 95 D 18 D 44.75 D 49 D 94 D 17 D 42.5 D 48 D 93 D 16 D 40.25 D 47 D 92 D 15 D 38 D 46 D 91 D 14 D 35.75 D 45 D 90 D 13 D 33.5 D 44 D 89 D 12 D 31.25 D 43 D 88 D 11 D 29 D 42 D 86.75 D 10 D 26.75 D 41 D 85.5 D 9 D 24.5 D 40 D 84.25 D 8 D 22.25 D 39 D 83 D 7 D 20 D 38 D 81.5 D 6 D 17.5 D 37 D 80 D 5 D 15 D 36 D 78.5 D 4 D 12.5 D 35 D 77 D 3 D 10 D 34 D 75.5 D 2 D 7.5 D 33 D 74 D 1 D 5 D 32 D 72.5 D % 0 D 2.5 D %
TB6613FTG 2012-01-30 25 application circuit example dc motor1 vm 2.5v to 5.5v r1= 0.5 ? + 10uf 0.1uf c3 c4 shutter coil mcu + 10uf 0.1uf c1 c2 vcc 3v to 5.5v gnd vcc h-bridge e eo2 eo1 rfe 6 mck ck data ld pre- driver stby fo2 fo1 pgnd1 stand by pwm tim er h-bridge control uvlo (2.2v) h-bridge f pre- driver h-bridge control 34 3 vm3 40 42 43 1 44 31 do2 do1 rfd pre- driver pwm tim er h-bridge control 1/n 19 17 18 24 pwmd /en2 h-bridge c co2 co1 rfc pre- driver pwm tim er h-bridge control 25 vm2 22 20 21 23 pwmc /ck2 step decorder 2 6bit dac h-bridge b bo2 bo1 rfb pre- driver pwm tim er h-bridge control 1/n 37 39 38 32 pwmb / en1 h-bridge a a o2 a o1 rfa pre- driver pwm tim er h-bridge control vm1 36 35 33 pwma / ck1 step decorder 1 6bit dac 1/n 2bit dac2 2bit dac1 6bit dac h-bridge d mo1 vref (0.3v) 5 7 8 28 29 27 30 mo2 26 ts d ho2 ho1 pre- driver h-bridge control 13 12 2 11 pwmh h-bridge g go2 go1 pgnd2 pre- driver h-bridge control 9 vm4 16 15 14 10 h-bridge h 4 12bit serial decoder pwmg pwmf pwme step mo to r1 r2= 0.5 ? step motor2 r3= 0.5 ? r4= 0.5 ? r5= 0.5 ? 41 step motor3
TB6613FTG 2012-01-30 26 package dimensions weight: 0.05 g (typ.)
TB6613FTG 2012-01-30 27 notes on contents 1. block diagrams some of the functional blocks, circ uits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. equivalent circuits the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. timing charts timing charts may be simplified for explanatory purposes. 4. application circuits the application circuits shown in this document ar e provided for reference purposes only. thorough evaluation is required, especially at the mass production design stage. toshiba does not grant any license to any industrial property rights by prov iding these examples of application circuits. 5. test circuits components in the test circuits are used only to obtain and confirm the devi ce characteristics. these components and circuits are not guaranteed to prev ent malfunction or failure from occurring in the application equipment. ic usage considerations notes on handling of ics (1) the absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings. exceeding the rating(s) may cause the device breakd own, damage or deterior ation, and may result injury by explosion or combustion. (2) use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or ic failure. the ic will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. to minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. (3) if your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfuncti on or breakdown caused by the cu rrent resulting from the inrush current at power on or the negative current result ing from the back electromotive force at power off. ic breakdown may cause injury, smoke or ignition. use a stable power supply with ics wi th built-in protection functions. if the power supply is unstable, the protection function may not operate, causing ic breakdown. ic breakdown may cause injury, smoke or ignition. (4) do not insert devices in the wrong orientation or incorrectly. make sure that the positive and negative terminals of power supplies are connected properly. otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. in addition, do not use any device that is applied th e current with inserting in the wrong orientation or incorrectly even just one time.
TB6613FTG 2012-01-30 28 points to remember on handling of ics (1) over current prot ection circuit over current protection circuits (referred to as cu rrent limiter circuits) do not necessarily protect ics under all circumstances. if the over current protection circuits operate against th e over current, clear the over current st atus immediately. depending on the method of use and usage condit ions, such as exceeding absolute maximum ratings can cause the over current protection circuit to not operate properly or ic breakdown before operation. in addition, depending on the method of use and usag e conditions, if over current continues to flow for a long time after operation, the ic may generate heat resulting in breakdown. (2) heat radiation design in using an ic with large current flow such as power amp, regulator or driver, please design the device so that heat is appropriately radiat ed, not to exceed the specified junc tion temperature (tj) at any time and condition. these ics generate heat even during normal use. an inadequate ic heat radiation design can lead to decrease in ic life, deterioration of ic characteristics or ic breakdown. in addition, please design the device taking into considerate the effect of ic heat radiation with peripheral components. (3) back-emf when a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor?s power supply due to the effect of back-emf. if the current sink capability of the power supply is small, the device?s motor powe r supply and output pins might be exposed to conditions beyond absolute maximum ratings. to avoid this problem, ta ke the effect of back-emf into consideration in system design.
TB6613FTG 2012-01-30 29 the following conditions apply to solderability: about solderability, following conditions were confirmed (1)use of sn-37pb solder bath solder bath temperature: 230cdipping time: 5 se condsthe number of times: onceuse of r-type flux (2)use of sn-3.0ag-0 .5cu solder bath solder bath temperature: 245cdipping time: 5 se condsthe number of times: onceuse of r-type flux
TB6613FTG 2012-01-30 30 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collect ively ?toshiba?), reserve the right to make changes to the in formation in this document, and related hardware, software a nd systems (collectively ?product?) without notice. ? this document and any information herein may not be reproduc ed without prior written permission from toshiba. even with toshiba?s written permission, reproduction is permissible only if reproduction is without alteration/omission. ? though toshiba works continually to improve product?s quality a nd reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for prov iding adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid sit uations in which a malfunction or failure of product could cause loss of human life, b odily injury or damage to property, including data loss or corruption. before customers use the product, create designs including the product, or incorporate the product into their own applications, customers mu st also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specificati ons, the data sheets and application notes for product and the precautions and conditions set forth in the ?toshiba semiconduc tor reliability handbook? and (b) the instructio ns for the application with which the product will be used with or for. customers are solely responsible for all aspects of their own product design or applications, including but not lim ited to (a) determining the appropriateness of the use of this product in such des ign or applications; (b) evaluating and dete rmining the applicability of any information contained in this document, or in charts, dia grams, programs, algorithms, sample application circuits, or any other referenced document s; and (c) validating all operating paramete rs for such designs and applications. toshiba assumes no liability for customers? product design or applications. ? product is intended for use in general el ectronics applications (e.g., computers, personal equipment, office equipment, measur ing equipment, industrial robots and home electroni cs appliances) or for specif ic applications as expre ssly stated in this document . product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality a nd/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or se rious public impact (?unintended use?). unintended use includes, without limit ation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equi pment used for automobiles, trains, ships and other transportation, traffic signalin g equipment, equipment used to control combustions or explosions, safety dev ices, elevators and escalato rs, devices related to el ectric power, and equipment used in finance-related fi elds. do not use product for unintended us e unless specifically permitted in thi s document. ? do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy product, whether in whole or in part. ? product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. ? the information contained herein is pres ented only as guidance for product use. no re sponsibility is assumed by toshiba for an y infringement of patents or any other intellectual property rights of third parties that may result from the use of product. no license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. ? a bsent a written signed agreement, except as provid ed in the relevant terms and conditions of sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liability whatsoever, including without limitation, indirect, co nsequential, special, or incidental damages or loss, including without limitation, loss of profit s, loss of opportunities, business interruption and loss of data, and (2) disclaims any and all express or implied warranties and conditions related to sale, use of product, or information, including warranties or conditions of merchantability, fitness for a particular purpose, accuracy of information, or noninfringement. ? do not use or otherwise make available product or related so ftware or technology for any m ilitary purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technolog y products (mass destruction weapons). product and related softwa re and technology may be controlled under the japanese foreign exchange and foreign trade law and the u.s. export administration regulations. export and re-export of product or related softw are or technology are strictly prohibited except in comp liance with all applicable export laws and regulations. ? please contact your toshiba sales representative for details as to environmental matters such as the rohs compatibility of pro duct. please use product in compliance with all applicable laws and regula tions that regulate the inclusion or use of controlled subs tances, including without limitation, the eu rohs directive. toshiba assumes no liability for damages or losses occurring as a result o f noncompliance with applicable laws and regulations.

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